Low power NoC buffer protection using error correction code

Network-on-Chip (NoC) is most widely used as a communication framework to connect various Intellectual Properties (IPs) in an Integrated Circuit (IC). As technology scales down, buffers present NoC Router are more prone Multiple Cell Upsets (MCUs). To overcome this, Error Correction Code (ECC) introduced Router. Inclusion of ECC increases the number redundant bits stored buffer for error correction. This impacts area, operational power and delay router. The work discusses about correction 6-adjacent data with help optimized scheme. proposes new method efficiently design H-Matrix, which construct ECC, so reduce total overhead constraints arising out ECC. scheme implemented using this 16-bit data. results obtained compared similar other ECC's uses same or lesser bits. synthesis result shows that requirement reduced by 7\ 2\ respectively higher capacity, when Triple Adjacent (TAEC) Code.